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DS2229 Word-Wide 8 Meg SRAM Stik
www.dalsemi.com
FEATURES
Organized as a high density 512k x 16 bit StikTM Fast access time of 85 ns Unlimited write cycles Employs popular JEDEC standard 80-position SIMM connector Full 10% operating range Read cycle time equals write cycle time Ultra-low standby current < 10 A Suitable for battery-backed applications
PIN ASSIGNMENT
1 1M SRAM 1M SRAM 1M SRAM 1M SRAM 80-PIN SIP STIK 80
DESCRIPTION
The DS2229 is an 8,388,608-bit low-power fully static Random Access Memory organized as a 524,888 word by 16 bits using CMOS technology. The device employs the popular JEDEC standard 80-pin SIMM connection scheme with no additional circuitry required. The device operates from a single power supply with a voltage input of 4.5 to 5.5 volts. The Chip Enable inputs ( CE0 , CE1 , CE2 , CE3 ) are used for device selection and can be used in order to achieve the minimum standby current mode which facilitates battery backup. The device provides a fast access time of 85 ns. The DS2229 maintains TTL levels over input voltage range 4.5V to 5.5V. The DS2229 is JEDEC pin compatible (see Figure 1) with flash EEPROM memory SIMM boards of similar density. 1 of 10 112099
DS2229
PIN DESCRIPTION Figure 1
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PIN NAME GND VCC NC
OE
WEH WEL
PIN # 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
PIN NAME NC NC NC NC A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GND GND DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8
PIN # 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
PIN NAME DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 NC VCC NC GND NC GND GND NC NC GND
NC CS NC NC NC NC NC NC NC NC NC NC NC NC
CE3 CE2 CE1 CE0
PIN NAME A0 - A16
WEL WEH OE
DESCRIPTION Address Input Write Enable Input Low Write Enable Input High Output Enable Input No Connect Chip Enable Input Chip Select Data Input/Output +5 Volts Ground
GND NC NC NC NC NC NC
NC
CE0
- CE3
CS DQ0 - DQ15 VCC GND
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DS2229
DS2229 STATIC RAM MODULE FUNCTION DIAGRAM Figure 2
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DS2229
ABSOLUTE MAXIMUM RATINGS*
Power Supply Voltage Input, Input/Output Voltage Operating Temperature Storage Temperature * -0.3V to +7.0V -0.3 to VCC +0.3V 0C to 70C -55C to +125C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
OPERATION MODE
MODE READ WRITE DESELECT STANDBY STANDBY
CE0 - CE3
CS H H H X L
OE
WE
A0 - A16 STABLE STABLE X X X
DQ - DQ15 DATA OUT DATA IN HIGH-Z HIGH-Z HIGH-Z
POWER ICC0 ICC0 ICC0 ICCS1, ICCS2 ICCS1, ICCS2
L L L H X
L X H X X
H L H X X
CAPACITANCE
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP MAX 64 80
(tA=25C)
UNITS pF pF NOTES
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage SYMBOL VCC VIH VIL MIN 4.5 2.0 -0.3 TYP 5.0 MAX 5.5
(tA= 0C to 70C)
UNITS V V V NOTES
VCC+0.3 0.8
DC CHARACTERISTICS
PARAMETER Input Leakage Current I/O Leakage Current Output High Current Output Low Current Standby Current Standby Current Operating Current SYMBOL IIL ILO IOH IOL ICCS1 ICCS2 ICCO
CE0 CE0
(tA= 0C to 70C; VCC= 5V 10%)
CONDITIONS 0V VIN VCC
CE0
MIN
MAX 8 8
UNITS A A mA mA
NOTES
- CE3 = VIH, 0V VI/O VCC VOH = 2.4V VOL = 0.4V - CE3 =2.0V tA=25C - CE3 VCC -0.3V tA=25C -1.0 2.1
8 10 100
mA A mA 9
- CE3 = 0.8V; Cycle=100 ns tA=25C
CE0
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DS2229
LOW VCC DATA RETENTION CHARACTERISTICS
PARAMETER VCC for Data Retention SYMBOL VDR MIN 2.0 TYP MAX UNITS V
(tA= 0C to 70C)
TEST CONTIDION CE0 - CE3 VCC -0.2V, CS VCC -0.2V or 0V CS 0.2V VIN 0V VCC = 3.0V, VIN 0V CE0 - CE3 VCC -0.2V, CS VCC -0.2V or 0V CS 0.2V tA =25C See Retention Waveform
Data Retention Current
ICCDR
-
1
8
A
Chip Deselect to Data Retention Time Operation Recovery Time
tCDR tR
0 5
-
-
ns ms
LOW VCC DATA RETENTION TIMING WAVEFORM (1) (CE0 - CE3 Controlled) Figure 3
SEE NOTE 5
LOW VCC DATA RETENTION TIMING WAVEFORM (2) (CS Controlled) Figure 4
SEE NOTE 5
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DS2229
PRODUCT CHARACTERISTICS
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DS2229
AC ELECTRICAL CHARACTERISTICS READ CYCLE
PARAMETER Read Cycle Time Access Time
OE
(0C to 70C; VCC = 5V + 10%)
MIN 85 TYP MAX 85 45 85 10 0 10 30 UNITS ns ns ns ns ns ns ns 8 8 NOTES
SYMBOL tRC tACC tOE tCO tCOE tOD tOH
to Output Valid to Output Valid or CE0 - CE3 to Output In Low-Z
CE0 - CE3 OE
Output High-Z from Deselection Output Hold from Address Change
AC ELECTRICAL CHARACTERISTICS WRITE CYCLE
PARAMETER Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High-Z from WE Output Active from WE Data Setup Time Data Hold Time from WE SYMBOL tWC tWP tAW tWR tODW tOEW tDS tDH MIN 85 65 0 10 0 5 35 0
(0C to 70C; VCC = 5V + 10%)
TYP MAX UNITS ns ns ns ns 30 ns ns ns ns 4 8 8 3 3 1 NOTES
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DS2229
READ CYCLE Figure 5
WRITE CYCLE 1 Figure 6
SEE NOTES 1, 3, 4, 6, 7, AND 9
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DS2229
WRITE CYCLE 2 Figure 7
NOTES:
1. A write occurs during the overlap of a low CE0 - CE3 , a high CS, and a low WE . A write begins at the latest transition among CE0 - CE3 going low, CS going high, and WE going low. A write ends at the earliest transition among CE0 - CE3 going high, CS going low and WE going high. tWP is measured from the beginning of write to the end of write. 2. WE is high for a read cycle. 3. tDS ends and tDH begins at the earliest transaction among CE0 - CE3 going high. 4. tWR is measured from the earliest of CE0 - CE3 or WE going high or CS going low to the end of write cycle. 5. CS controls address buffer, WE buffer, CE0 - CE3 buffer, OE buffer and DIN buffer. If CS controls data retention mode, VIN levels (address, WE , OE , CE0 - CE3 , I/O) can be in the high impedance state. If CE0 - CE3 controls data retention mode, CS must be CS VCC - 0.2V or 0V < CS < 0.2V. The other input levels (address, WE , OE , I/O) can be in the high impedance state. 6. If CE0 - CE3 goes low simultaneously with WE going low or after WE going low, the outputs remain in a high impedance state. 7. If CE0 - CE3 is low and CS is high during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 8. This parameter is sampled and not 100% tested. 9. Only one CE active during any read or write cycle.
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DS2229
DS2229 80-PIN SIP STIK
PKG DIM A B C D E F G H I J K L M N O P
80-PIN MIN 4.645 4.379 0.729 0.395 0.245 MAX 4.655 4.389 0.739 0.405 0.255
0.050 BSC 0.075 0.245 0.085 0.255
1.950 BSC 0.120 2.320 2.445 0.057 0.130 2.330 2.455 0.067 0.130 0.130 0.054
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